1. Field of the Invention
The present invention relates to interconnect structures and, more particularly, to a method of forming a through-the-wafer metal interconnect structure.
2. Description of the Related Art
An integrated circuit or chip that includes through-the-wafer metal interconnect structures can be used, for example, to electrically connect a number of integrated circuits or chips that are vertically stacked on top of each other to form a device with a substantially smaller footprint. In addition, through-the-wafer metal interconnect structures can also improve the pad layout density, and even provide backside integration opportunities.
One method of forming a through-the-wafer metal interconnect structure is to first form a trench in the wafer. Once the trench has been formed, a barrier layer and a copper seed layer are subsequently formed in the trench. After the copper seed layer has been formed, a conductive metal layer is electroplated over the seed layer to fill up the trench.
The conductive metal layer, the seed layer, and the barrier layer are then planarized to remove the barrier layer from the surface of the wafer. The planarization step forms a conductive plug that lies in the trench and extends into the wafer. After the remainder of the integrated circuits have been formed on the wafer, the bottom surface of the wafer is planarized or ground down until the bottom surface of the conductive plug is exposed.
FIG. 1 shows a cross-sectional view that illustrates a prior-art, trench-based, through-the-wafer structure 100 prior to the planarizing or grinding step that exposes the bottom side of the conductive plug. As shown in FIG. 1, structure 100 includes a wafer 110, and a trench 112 that is formed in wafer 110.
In addition, as further shown in FIG. 1, structure 100 includes a barrier layer 114 that is formed on wafer 100 to line trench 112, and a copper seed layer 116 that is formed on barrier layer 114. Further, structure 100 includes a copper plug 118 that is electroplated on seed layer 116 to fill up trench 112.
One drawback to a trench-based, through-the-wafer structure is that it is difficult to form barrier layer 114 and copper seed layer 116 with adequate step coverage when the aspect ratio exceeds approximately 4:1, i.e., the depth of the trench is more than four times the width of the trench.
As further shown in FIG. 1, as the depth of trench 112, and thereby the aspect ratio, increases, the thicknesses of barrier layer 114 and copper seed layer 116 decrease. Thus, the quality of the step coverage over trench 112 decreases as the depth of trench 112 increases.
In addition to two layers of material that get thinner as the depth of trench 112 increases, another draw back of a trench-based through-the-wafer structure is that a number of voids, such as void 120, can be formed when a copper solute is electroplated to form copper plug 118. Preferably, barrier layer 114, copper seed layer 116, and copper plug have a uniform thickness with no voids.
One solution to this drawback is to form a through-the-wafer hole rather than forming a plug in a trench, and then exposing the bottom surface of the plug. For example, a through-the-wafer hole can be formed by first forming and patterning a hard mask over the surface of the wafer. The exposed regions are then dry etched, such as with a plasma etcher, using, for example, the Bosch process, until a hole has been formed completely through the wafer.
After the through-the-wafer holes have been formed, a barrier layer is formed on the wafer in the openings. Following this, a copper seed layer is formed on the barrier layer in the openings. Once the copper seed layer has been formed, a copper metal solute is electroplated to the copper seed layer to form a copper plug.
One drawback with forming through-the-wafer holes using dry etching processes is that it takes a significant amount of time for a dry etching process to form a hole through the wafer. As a result, to maintain production-level fabrication rates, additional dry etching equipment is required which, in turn, substantially increases the cost of the wafers.
Thus, there is a need for a method of forming a through-the-wafer hole which takes less time and requires less expense than conventional dry etching processes.